This application claims the priority of an application No. 201710702610.X filed on Aug. 16, 2017, entitled “GOA driving circuit and LCD device”, the contents of which are hereby incorporated by reference.
Field of Invention
The present invention relates to a liquid crystal display (LCD), and more particularly to a gate driver on array (GOA) driving circuit and a LCD device.
Description of Prior Art
The liquid crystal display device has become a display device of mobile communication devices, PCs, TVs and the like due to its advantages of high display quality, low price and convenient portability. The conventional LCD device driving technology tends to adopt GOA technology, GOA technology can simplify the manufacturing process of flat display panel, eliminate the need of bonding process of horizontal scanning line, improve productivity, reduce product cost, and enhance the integration of the display panel for making the display panel more suitable for the production of narrow border or borderless display products, to meet the needs of modern people.
GOA technology (gate driver on array technology), the gate line scan driving signal circuit is fabricated on an array substrate by using an existing thin film transistor (TFT) LCD array process to realize a scan driving method of gate-by-gate. The conventional GOA driving circuit comprises a plurality of cascaded GOA units. FIG. 1 is a circuit diagram of an Nth-stage GOA unit of a conventional art. Referring to FIG. 1 the Nth-stage GOA unit comprises a pull-up control unit 110, a pull-up unit 120, a pull-down unit 130, a pull-down sustaining unit 140, a download unit 150 and a bootstrap capacitor unit 160.
The pull-up unit 120 comprises a third transistor T3, and is mainly responsible for outputting a clock signal CK to an Nth-stage horizontal scanning line G(n) of the display region. The pull-up control unit 110 comprises a first transistor T1, and is responsible for controlling the turn-on time of the pull-up unit 120. A previous-stage download signal ST(n−1) or a start signal STV is inputted to a gate electrode and a source electrode of the first transistor T1 and a drain electrode of the first transistor T1 is connected with a first node Q(n). The pull-down unit 130 comprises transistors T4 and T5, and is responsible for pulling down the horizontal scanning signal on the Nth-stage horizontal scanning line G(n) to low level, that is, turning off the horizontal scanning signal. A next-stage download signal ST(n+1) is inputted to gate electrodes of the transistors T4 and T5. The pull-down sustaining unit 140 is responsible for maintaining the horizontal scanning signal on the Nth-stage horizontal scanning line G(n) and the first node Q(n) in the off state (i.e., the negative potential). The bootstrap capacitor unit 160 is responsible for the second rising of the potential of the first node Q(n), which facilitates the output of the pull-up unit 120. The download unit 150 is responsible for outputting a current-stage download signal ST(n). VSS indicates a DC low level.
FIG. 2 is a waveform diagram of each node or each output terminal of the conventional art. It can be seen from FIG. 2 that the second node K(n) is at a high level during most of each cycle of the GOA driving circuit, which causes the sixth TFT T6 and the seventh TFT T7 to be subjected to long-term positive bias temperature stress(PBTS), the threshold voltages of the sixth TFT T6 and the seventh TFT T7 are seriously shifted in the positive direction. After long-term operation, the threshold voltages of the sixth TFT T6 and the seventh TFT T7 are too high, resulting in insufficient opening of the sixth TFT T6 and the seventh TFT T7. As a result, the first node Q(n) and the horizontal scanning signal of the Nth-stage horizontal scanning line G(n) are abnormal, resulting in failure of the GOA driving unit.